FIG. 1 is a schematic block diagram of a conventional synchronous dynamic random access memory (“SRAM”).
An SDRAM includes a plurality of memory banks in a core area of the SDRAM. In FIG. 1, the SDRAM includes, for example, two memory banks Bank 0 70 and Bank 1 75. Each memory bank includes a plurality of memory cells, each connected between one of a plurality of bit lines BL and one of a plurality of word lines WL.
The SDRAM includes a controller 10, a mode register 20, an address buffer 30, a bank selector 40, row address decoders 50 and 55, column address decoders 60 and 65, and a data input/output buffer 90 in a peripheral area of the SDRAM.
The controller 10 includes a command decoder 12, a refresh counter 18, and a control logic 14. The command decoder 12 receives: a clock signal CLK; a clock enable signal CKE; and a control signal 13, such as a chip enable signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, and the like, from an external memory controller (not shown), and generates various commands including an activation command, a read command, a write command, an auto-refresh command, and a power-down command. The control logic 14 controls operation modes of the SDRAM according to data (e.g., CAS latency, burst type, and burst length) from the mode register 20 for controlling the SDRAM operation modes and the commands for controlling the SDRAM operation modes. The refresh counter 18 controls a refresh operation of DRAM cells in the memory cell arrays under control of the control logic 14.
The address buffer 30 includes an address register 32 and a bank controller 34.
The address register 32 receives and latches an address 31, and outputs a row address, a column address, and bank information at a given timing in response to the activation command, the read command, the write command, and the auto-refresh command.
The bank controller 34 generates bank select signals based on the bank information (BA) 33 and controls the row address decoder of the selected one of the plurality of banks to perform operation in response to the row address and the column address decoder of the selected one of the plurality of banks to perform operation in response to the column address.
A column address selector 42 provides the column address to the column address decoder of the bank selected by the bank select signal 37. A row address selector 44 provides the row address to the row address decoder of the bank selected by the bank select signal 37.
The SDRAM may include a row address decoder and a column address decoder for each memory bank. The row address decoders 50 and 55 decode the row address 41 to activate one of the plurality of word lines of the banks 70 and 75. The column address decoders 60 and 65 decode the column address 43 to activate one of the plurality of bit lines of the banks 70 and 75.
Charges of a memory cell connected with the activated word lines are carried on a corresponding bit line pair BL and BL/, and a difference in voltage between bit line pairs is sensed and amplified by a bit-line sense amplifier (not shown). After a predetermined time lapses, data developed on the bit line pair activated by the column address decoder is output to an I/O line pair and then to an I/O sense amplifier (not shown) and the input/output buffer 90.
When the read command is activated, the data input/output buffer 90 reads data (DQ) from the memory cell array and supplies the data (DQ) to an external data bus. When the write command is activated, the data input/output buffer 90 receives data (DQ) from the external data bus and supplies the data (DQ) to the memory cell array.
Inter-bank self-copy is not supported by a conventional SDRAM. Accordingly, an external processor should directly access the SDRAM to read data from a specific bank of the SDRAM and write the read data to another bank of the SDRAM. During the external processor accesses the SDRAM, the external processor cannot perform other operations, resulting in low operation speed and low operation performance.
In particular, for the purpose of multitasking, when a dual-core CPU having first and second processors mounted on one die accesses, via one port, a conventional single-port SDRAM without self-copy function, e.g., when an MPEG4 engine in the processor is allowed to access a specific memory area, the processor having the MPEG4 engine should directly access the SDRAM to read data and write the data to the specific memory area and then the MPEG4 engine should access the specific memory area. Thus, the processor having the MPEG4 engine is not able to perform other operations while the processor accesses the data, thereby degrading operation performance of the processor.
A conventional dual-port SDRAM includes a first local memory area dedicated to the first processor, a second local memory area dedicated to the second processor, and a shared memory area shared by the first and second processors. The conventional dual-port SDRAM further includes a hardware semaphore for controlling the first processor and the second processor to access the shared memory area without a collision. When an authority for accessing the shared memory area is changed, the hardware semaphore informs the first processor and the second processor of the authority change using a ready signal. In this case, the first and second processors read and write specific data from and to the hardware semaphore in order to access the shared memory area, causing overhead in accessing the shared memory area.
Inter-bank self-copy is not supported by a conventional dual-port SDRAM. Accordingly, when the conventional dual-port SDRAM is applied to a mobile communication terminal having a baseband processor and an application processor, the application processor should access the shared memory area every time when the data written to the shared memory area by the baseband processor need to be read several times by the application processor. This causes overhead in occupying the hardware semaphore, thereby degrading overall performance.